1. Field of the Invention
Embodiments of the invention relate to auto-zero amplifiers and a feedback amplifier circuits using auto-zero amplifiers.
2. Related Art
FIGS. 8A-8C illustrate circuit diagrams showing a circuit configuration and operations of the circuit of an auto-zero amplifier as an OP (operational) amplifier circuit according to the related art.
The operations of the circuit of the auto-zero amplifier according to related art shown in FIG. 8(A) may be classified into two phases, one of which is a compensation phase as shown in FIG. 8(B) and the other one of which is an operation (actual use) phase as shown in FIG. 8(C).
First, the operation in the compensation phase shown in FIG. 8(B) will be explained. In the compensation phase shown in FIG. 8(B), with switches SW_A shown in FIG. 8(A) being closed, switches SW_B shown in FIG. 8(A) are opened. At this time, the circuit shown in FIG. 8(A) comes to form a voltage follower to an input voltage to a non-inverting (+) input terminal. The input voltage to the voltage follower circuit shown in FIG. 8(B), being 0 volt, causes an offset voltage of the OP amplifier circuit to be produced in the output voltage. Since the output terminal of the OP amplifier circuit is connected to the ground (GND) through a capacitor, the capacitor is charged by the offset voltage of the OP amplifier circuit.
Following this, the operation in the operation (actual use) phase shown in FIG. 8(C) will be explained. In the operation phase shown in FIG. 8(C), with switches SW_A shown in FIG. 8*(A) being opened, switches SW_B shown in FIG. 8(A) are closed. Then, the offset voltage due to the capacitor charged in the compensation phase shown in FIG. 8(B) and the offset voltage of the OP amplifier circuit shown in FIG. 8(C) come to be voltages canceled each other out to therefore produce no offset voltage in the output voltage of the OP amplifier circuit in the operation phase shown in FIG. 8(C), by which a highly accurate output voltage of an OP amplifier circuit can be obtained.
Incidentally, in Japanese Patent Application Publication No. JP-A-62-292013, a comparator circuit is disclosed, in which an OP amplifier circuit is used that produces no offset voltage in the output voltage similarly to the OP amplifier circuit shown in (A) of FIG. 8.
Moreover, in Japanese Patent Application Publication No. JP-A-2005-020291, an OP amplifier circuit is disclosed in which two OP amplifier circuits, each being similar to the OP amplifier circuit shown in FIG. 8(A), are prepared to make them alternately carry out a compensation operation and a normal operation between the two so as to thereby eliminate the time in which no normal operation is carried out.
With the related art as shown in FIGS. 8(A)-8(C), the operations of the OP amplifier circuit are periodically switched in order as “the compensation phase”→“the operation phase”→“the compensation phase”→“the operation phase”→ . . . , which therefore periodically produces a time in which the OP amplifier circuit is not operated as an OP amplifier circuit. In order to avoid this, there is an idea of bringing the operation of the OP amplifier circuit into the compensation phase only at the turning-on of the power supply so as to compensate the offset voltage and thereafter into the operation phase so as to continue the operation in the operation phase, for example. This, however, has a problem in that the compensation of the offset voltage due to a temperature drift becomes impossible. As another countermeasure, there is one in which two auto-zero amplifiers as OP amplifier circuits are prepared as shown in Japanese Patent Application Publication No. JP-A-2005-020291 for alternately switching the outputs thereof, for example. This, however, has a problem in that two auto-zero amplifiers are required to result in an increase in the scale of the circuit. Thus, certain problems and shortcomings exist in the related art.